1. Field of the Invention
The present invention relates to an image processing apparatus for processing image signals obtained by reading an original image with line image sensors such as CCD's.
2. Related Background Art
The assigned of the present invention has already proposed, in U.S. patent application Ser. No. 798,672, filed Nov. 15, 1985, an image reading apparatus of serial scanning process, in which a linear image sensor, having a reading area shorter than the width of original image, is employed and is moved in a sub scanning direction after each main scanning operation to read the entire original image area.
FIG. 1 illustrates the image reading operation of such serial scanning image reading apparatus.
A linear image sensor 1, composed of a CCD, scans a reading area RA by a movement along the illustrated trajectory, starting from a home position HP, by means of an unrepresented main scanning drive system for moving said CCD image sensor 1 in the main scanning direction and an unrepresented sub-scanning drive system for moving said sensor in the sub-scanning direction. The reading area RA is read in succession in the order of scans (1) to (5), so that the entire reading area is read by plural main scanning operations.
In such image reading apparatus, the image variable magnification processing, such as image reduction or enlargement, is generally achieved, in the main scanning direction, by a mechanical method of varying the scanning speed, or the moving speed of the CCD image sensor 1, in accordance with the rate of image size variation (variable magnification), and, in the sub scanning direction of the scanning direction of CCD, by an electrical variable magnification method of thinning out or padding image data.
In a case where the number of image data in the scanning direction of CCD is variable and the charge accumulating time of CCD is constant and continuous, an image size reduction to 50% can be achieved by doubling the moving speed of the CCD image sensor 1 in the main scanning direction, compared to the speed in the equal image size reading, and by thinning out every other pixel of the image data in the CCD scanning direction. On the other hand, an image size enlargement to 200% can be achieved by reducing the moving speed of the CCD image sensor 1 in the main scanning direction to a half compared to the speed in the equal image size reading, and by repeating every pixel twice, in the image data in the CCD scanning direction.
In such neat image magnification as 50% or 200%, i.e., where the magnification is an integer or the inverse of an integer, the image connecting process for maintaining the continuity of image at the boundaries of the scans (1) to (5) is relatively simple, but, for such image magnification as 59% or 167%, there is required a very complex process for the image connection. Also, if an additional image processing such as smoothing is conducted after the image size variation, image data before and after the processed pixel are additionally required and the image connection at such image size variation becomes even more complex.
FIG. 2 shows an example of electric image size varying circuit for thinning out or padding image data.
Input image data are alternately stored in random access memories (RAM) 13, 15. The image size reduction is achieved by thinning out image data at the storage thereof into said memories, while the image size enlargement is achieved by padding the image data at reading from said memories, and the obtained output image data are supplied to a following circuit.
A D-type flip-flop (DFF) 10 is provided for latching the input image data, by means of an image clock signal WRCK supplied in synchronization with the input image data.
A decimal rate multiplier (DRM) 11 thins out the image clock signal WRCK to generate a clock signal WRCM for image size reduction. It is composed for example of an SN74167, a standard TTL device supplied by Texas Instruments, and generates a thinned out clock signal WRCM according to a binary coded decimal number such as "99" or "55" set at a data input terminal. Since said device SN74167 is unable to transmit the image clock signal WRCK without change, an external circuit is added to enable signal transmission in case image size reduction is not conducted. A synchronization signal WRST, for synchronization of every line, clears a counter incorporated in the DRM 11 upon shifting to the low level state, whereby the image clock signal WRCK is thinned out in the same manner during the period of a main scanning operation.
A counter 12 generates the write-in addresses for the RAM 13, 15, and counts upward from zero in response to the synchronization signal WRST.
A D-type flip-flop 18, for latching the data read from the RAM 13, 15 and selected by a selector 17, latches the data by an external image clock signal RDCK.
A binary rate multiplier (BRM) 19 thins out the image clock pulses RDCK to generate clock pulses RDCM for image enlargement. It is composed for example of an SN7497, a standard TTL device supplied by Texas Instruments, and generates thinned out pulses RDCM according to a binary number such as "6FF" or "955" (hexadecimal) set at a data input terminal. Since said device SN7497 is unable to transmit the image clock pulses RDCK without change, an external circuit is added in order to enable signal transmission in case image size enlargement is not conducted. A synchronization signal RDST, for synchronization of every line, clears a counter incorporated in the BRM 19 upon shifting to the low level state, whereby the image clock pulses RDCK are thinned out in the same manner during the period of a main scanning operation.
A counter 20 generates the read-out addresses for the RAM's 13, 15, and counts upward from zero in response to the synchronization signal RDST.
The RAM's 13, 15 execute writing and reading of the image data according to the write-in addresses of the counter 12 or the read-out addresses of the counter 20, selected by selectors 14, 16, and constitute so-called double buffer in which a RAM effects data writing while the other effects data reading.
In the above-explained structure, image data thinned out corresponding to the rate of image reduction are stored in the RAM's 13, 15 by forming the write-in addresses according to the clock pulses WRCM obtained by thinning out, according to the rate of image reduction, the image clock pulses WRCK entered in synchronization with the input image data. Also image data padded corresponding to the rate of image enlargement are obtained from the latch 18, by forming the read-out addresses for the RAM's 13, 15 according to the clock pulses RDCM obtained by thinning out the image clock pulses RDCK corresponding to the rate of image enlargement.
FIG. 3 illustrates an image connecting process at an image size variation.
In FIG. 3, an upper row shows the state of the image reading line when the reading area is viewed in the CCD scanning direction (sub-scanning direction) in FIG. 1, or the state of output pixels in the equal-size image reading operation. The pixels a, b, c and d are those involved in the image connecting operation between an l-th scanning and an (l+1)-th scanning, and, in the present example, a smoothing process by a 3.times.3 matrix is to be applied by a following circuit.
A lower row in FIG. 3 shows the state of output pixels in case of an image enlargement to 150%. Pixels a', a", b', c', c" and d" respectively correspond to pixels a, b, c and d padded to 150%.
In the present example, in the case of an image enlargement to 150%, it is necessary to release pixels a', a", b', c', c" in the l-th scanning and pixels a", b', c', c", d" in the (l+1)-th scanning. The method of image connection is variable according to the number of pixels of the CCD image sensor 1 and the image magnification, so that the positions of pixels to be padded or thinned out have to be modified accordingly.
In order to achieve exact image connection as shown in FIG. 3 with the circuit structure shown in FIG. 2, the outputs of the incorporated counters of the DRM 12 and BRM 19 have to coincide each other at the image connecting position, and, for this purpose, it becomes necessary to control exact data on the image size variation such as the counter presetting and the counter reading at the image connecting position, in addition to the counter clearing. Consequently the circuit inevitably becomes large and complex.
Also an additional circuit becomes necessary for effecting the writing and reading of the image data at an arbitrary timing after the entry of the synchronization signals WRST, RDST.
However, if the image data are thinned out or padded independently for each main scanning operation, the pitch of thinned out or padded pixels may become different, at the junction of the data obtained from the l-th main scanning and those from the (l+1)-th main scanning, from that in other parts, so that the output image may become distorted at such junction.